Determine the final output states over time for the following circuit, built from D-type gated latches:
At what specific times in the pulse diagram does the final output assume the input's state? How does this behavior differ from the normal response of a D-type latch?
uploaded by (dinesh)
We have a decoder with 3 inputs which may be a,b,c and eight active low outputs 0 to 7 . In addition to this there is a active low enable input EN' .We wish to implement the following function using the decoder and a few NAND gates as possible.....show the block diagram..........
f(a,b,c,e)= Em(1,3,7,9,15)
(E----- summation....)
posted by (dinesh)
We wish to build a 32 way active decoder,using only the four - way decoders as given below the inputs may be named as v,w,x,y,z and outputs may be given as 0 to31 posted by (dinesh)